module Breg(

        input [31:0] D,
        input clk,
        output [31:0] Q
    );

    reg [31:0] B_reg;

    // Initialize register
    initial begin
        B_reg = 32'd0;
    end

    // Write register
    always @(posedge clk) begin
        B_reg <= D;
    end

    // Read register
    assign Q = B_reg;

endmodule
